Hui-Ling Zhen

Hui-Ling Zhen

AI for Verification | AI for EDA | LLM Reasoning | Self-evolve Agent

I am currently a Member of Technical Staff in Agentrys (San Jose), working as the core builder of the self-evolving agent in chip design, testing, and verification. Before that, I worked as a Senior Research Staff (Level-19) at Huawei, Hong Kong. My work focuses on agent algorithms and their applications in industrial EDA, including ATPG, LEC, formal verification, and coverage-guided testbench generation. Before joining Huawei in 2019, I was a Postdoctoral Research Fellow at City University of Hong Kong, where I worked on learning to optimize and solver applications in large-scale industrial problems. Earlier, I received my Ph.D. from Beijing University of Posts and Telecommunications in 2016.

I am deeply interested in agent algorithms, complex optimization, and building effective agent for testing and verification, as well as better chip design. If you share similar interests, please feel free to reach out.

"Do not go gentle into that good night."

Hui-Ling Zhen profile photo

Experience

  1. 2026 - Present, Agentrys, San Jose, California, USA.
    Member of Technical Staff. Working on AI for chip design, testing, and verification.
  2. 2019 - 2026, Huawei Noah's Ark Lab / Foundation Model Department, Hong Kong.
    Research Scientist, 2019-2021; Staff Researcher, 2021-2024; Senior Staff Researcher, 2025-2026.
  3. 2018 - 2019, City University of Hong Kong.
    Postdoctoral Research Fellow working on optimization, machine learning, and related algorithmic foundations.

Selected Research

Selected projects and related papers. Please see my Google Scholar for the full and latest publication list.

LLM/Agent for Testing & Verification

Highlights

Built LLM-driven and agentic verification workflows for Verilog generation, bug finding, tool invocation, verifier feedback, and coverage-guided testbench generation.

Selected Projects

  • Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation, arXiv 2026 | paper | code
    A tool-grounded self-evolution framework for Verilog generation, using simulator, synthesis, timing, downstream feedback, and reusable RTL skills to improve generated RTL.
  • Agentic ATPG | code
    The first agent-powered ATPG algorithm. Agent can first optimize and evaluate command-line configurations from outside the tool, then later make controlled white-box changes to the core algorithm once the evaluation loop is reliable.
  • Agentic Verification | code
    LLM-powered Agentic Verification for hardware. The core bilevel architecture is constructed by CodeX and veriagent (our runtime). VeriAgent does not try to replace Codex as a general-purpose coding agent. Instead, it supervises Codex with explicit workflow stages, deterministic Checkers, verification-domain MCP tools, human checkpoints, and a measurable run_manifest.json.

Related Papers

  1. BetterV: Controlled Verilog Generation with Discriminative Guidance, ICML 2024 | paper
    Developed a generator-discriminator training framework for 7B RTL code generation; even two years after release, it remains a same-size SOTA for correctness and outperforms several models larger than 14B.
  2. DiLA: Enhancing LLM Tool Learning with Differential Logic Layer, KDD 2026 | paper
    Introduced a way to make the solver act as a differentiable layer that interacts with the language model, outperforming tool-call-only solver integration and improving success rates across multiple industrial scenarios.
  3. SATformer: Transformer-Based UNSAT Core Learning, ICCAD 2023 | paper

AI for EDA (Formal Verification & Testing)

Highlights

Developed AI-driven SAT solving, preprocessing, conflict management, data augmentation, and learning-aided verification methods for industrial EDA workflows. Applications include ATPG, LEC, model checking, bug finding, and coverage improvement in real chip verification scenarios.

  • First industrial-grade learning-driven solver enhancement: explored learning-driven ways to modify and enhance solver internals for industrial verification problems, improving practical solving performance beyond black-box solver selection.
  • First industrial-grade GAN-based data synthesis for EDA: introduced generative data synthesis to improve the robustness of AI-driven verification methods under the data scarcity common in industrial EDA scenarios.
  • First industrial-grade circuit-level SAT direction: moved beyond conventional CNF-centric modeling by constructing circuit-level SAT solving directly over circuits, enabling ATPG to serve as a solver for industrial LEC and contribute meaningfully to datapath proofs.

Related Papers

  1. Accelerate SAT-Based ATPG via Preprocessing and New Conflict Management Heuristics, ASP-DAC 2021 | paper
  2. Neural Fault Analysis for SAT-Based ATPG, ITC 2022 | paper
  3. Conflict-Driven Structural Learning Towards Higher Coverage Rate in ATPG, ETS 2023 | paper
  4. HardSATGEN: Understanding the Difficulty of Hard SAT Formula Generation and a Strong Structure-Hardness-Aware Baseline, KDD 2023 | paper
  5. HardCore Generation: Generating Hard UNSAT Problems for Data Augmentation, NeurIPS 2024 | paper
  6. DeepGate2: Functionality-Aware Circuit Representation Learning, ICCAD 2023 | paper
  7. DiffSAT: Differential MaxSAT Layer for SAT Solving, ICCAD 2024 | paper
  8. Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving, DAC 2025 | paper

LLM Reasoning & Agentic LLMs

Highlights

Worked on long-context training, post-training, agent self-evolution, reasoning data construction, verifier-based optimization, and training-inference co-design for agentic LLMs. Achieved up to 8x end-to-end speedup in deep research agents and up to 20% improvement on long-context and agent benchmarks.

Related Papers

  1. LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration, DAC 2025 | paper
  2. TrimR: Verifier-Based Training-Free Thinking Compression for Efficient Test-Time Scaling, ICLR 2025 | paper
  3. Accelerating Large Language Model Reasoning via Speculative Search, ICML 2025 | paper
  4. HyperTree Planning: Enhancing LLM Reasoning via Hierarchical Thinking, ICML 2025 | paper
  5. DLLM Agent: See Farther, Run Faster, arXiv 2026 | paper
  6. SCOPE: Prompt Evolution for Enhancing Agent Effectiveness, arXiv 2025 | paper
  7. Towards Efficient Agents: A Co-Design of Inference Architecture and System, arXiv 2025 | paper
  8. MOSS: Efficient and Accurate FP8 LLM Training with Microscaling and Automatic Scaling, arXiv 2025 | paper
  9. CMoE: Fast Carving of Mixture-of-Experts for Efficient LLM Inference, ACL 2026 | paper

Learning to Optimize and Solver Intelligence

Highlights

Studied learning-to-optimize methods, solver intelligence, and machine learning techniques for large-scale industrial optimization and mixed-integer programming.

Related Papers

  1. Pareto Multi-Task Learning, NeurIPS 2019 | paper
  2. Learning to Select Cuts for Efficient Mixed-Integer Programming, Pattern Recognition 2022 | paper
  3. A Survey for Solving Mixed Integer Programming via Machine Learning, Neurocomputing 2023 | paper
  4. Bilevel Learning for Large-Scale Flexible Flow Shop Scheduling, Computers & Industrial Engineering 2022 | paper
  5. Machine Learning Methods in Solving the Boolean Satisfiability Problem, Machine Intelligence Research 2023 | paper

Awards and Honors

  1. Huawei Gold Medal Team Award, 2022.
  2. Huawei Gold Medal Individual Award, 2023 and 2024 (Top 1%).
  3. Field Hero Award for Critical Projects, 2023 and 2024 (Top 1%).
  4. Outstanding Business Contribution Award, 2024 and 2025.
  5. Huawei Innovation Pioneer Award, First Prize in 2022 and Second Prize in 2024.
  6. Huawei Hong Kong Research Center Director Award, 2024 and 2025.
  7. Outstanding Graduate Award, Beijing University of Posts and Telecommunications.